Exemplary embodiments of the present invention relate to a circuit and method for generating a power-up signal for initializing a semiconductor device.
Semiconductor devices, such as Dynamic Random Access Memory (DRAM), generally include a power-up signal generation circuit to secure stable operation of an internal circuit. When an is external power voltage VDD is inputted into a semiconductor device, the external power voltage VDD gradually increases to a target level. If the external power voltage VDD below the target level is supplied to a semiconductor internal circuit, a latch-up phenomenon may occur and the semiconductor device may be damaged. To prevent this phenomenon from occurring, a power-up signal generation circuit is implemented with the semiconductor device. The power-up signal generation circuit enables a power-up signal when the external power voltage VDD reaches the target level in order to stably operate the internal circuit and initialize the semiconductor device.
FIG. 1 is a schematic diagram illustrating a conventional power-up signal generation circuit, and FIG. 2 shows waveforms of an external power voltage VDD and a power-up signal PWRUP in the power-up signal generation circuit of FIG. 1.
The external power voltage VDD supplied to the power-up signal generation circuit is divided through resistors R11 and R12. The divided voltage is the voltage at a dividing node DIV. The divided voltage has a characteristic that it linearly varies according to the external power voltage VDD.
An NMOS transistor N11 receives the divided voltage as a gate input and is turned on more strongly as the level of the external power voltage VDD becomes higher. As the NMOS transistor N11 is turned on more strongly, a detection voltage becomes lower gradually. The detection voltage is the voltage at a detection node DET. When the detection voltage is lower than a certain level, that is, when the external power voltage VDD becomes higher than a target level V1, an inverter enables a power-up signal PWRUP.
Referring to FIG. 2, variation of the power-up signal PWRUP based on the variation of the external power voltage VDD is described herein, along with the concerns of the conventional technology for the power-up signal PWRUP.
In a duration prior to t1, the external power voltage VDD, which is applied to a circuit to turn on the power of a semiconductor device, is gradually increased. However, since the external power voltage VDD has not yet reached the target level V1, the power-up signal PWRUP is in a disabled state.
In a duration between t1 and t2, the external power voltage VDD is increased higher than the target level V1. The NMOS transistor N11 is turned on enough to enable the power-up signal PWRUP and the power-up signal PWRUP transitions to the same level as the external power voltage VDD.
In a duration between t2 and t3, the current consumption amount of the semiconductor device is increased and the external power voltage VDD drops. For example, when a DRAM performs an active operation ACT, such voltage drop may occur. In this case, when the external power voltage VDD drops lower than the target level V1, the detection voltage may be raised. When the detection voltage is raised and then drops, the power-up signal PWRUP is reset RESET and accordingly the semiconductor device in the middle of an operation may be inadvertently initialized again.